CATALOGO DEI PRODOTTI DELLA RICERCA

PRAVADELLI, Graziano
 Distribuzione geografica
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Continente #
NA - Nord America 5.515
EU - Europa 4.370
AS - Asia 1.993
AF - Africa 28
SA - Sud America 28
OC - Oceania 15
Continente sconosciuto - Info sul continente non disponibili 6
Totale 11.955
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Nazione #
US - Stati Uniti d'America 5.482
GB - Regno Unito 1.399
CN - Cina 1.089
SG - Singapore 627
IT - Italia 483
SE - Svezia 473
RU - Federazione Russa 386
FI - Finlandia 381
IE - Irlanda 350
FR - Francia 346
DE - Germania 310
UA - Ucraina 90
HK - Hong Kong 66
BE - Belgio 64
KR - Corea 54
VN - Vietnam 42
CA - Canada 26
NL - Olanda 25
PH - Filippine 24
TG - Togo 20
IN - India 19
TW - Taiwan 19
BR - Brasile 14
ID - Indonesia 14
TR - Turchia 12
AU - Australia 11
AT - Austria 8
IL - Israele 8
MX - Messico 7
PE - Perù 6
PL - Polonia 6
EE - Estonia 5
EU - Europa 5
JP - Giappone 5
NO - Norvegia 5
CL - Cile 4
ES - Italia 4
KE - Kenya 4
NZ - Nuova Zelanda 4
AL - Albania 3
CH - Svizzera 3
CZ - Repubblica Ceca 3
LU - Lussemburgo 3
LV - Lettonia 3
MD - Moldavia 3
PT - Portogallo 3
BG - Bulgaria 2
DK - Danimarca 2
EG - Egitto 2
GR - Grecia 2
HU - Ungheria 2
RO - Romania 2
A2 - ???statistics.table.value.countryCode.A2??? 1
AM - Armenia 1
AZ - Azerbaigian 1
BD - Bangladesh 1
BN - Brunei Darussalam 1
BY - Bielorussia 1
CO - Colombia 1
EC - Ecuador 1
IR - Iran 1
KG - Kirghizistan 1
KZ - Kazakistan 1
LK - Sri Lanka 1
LT - Lituania 1
MA - Marocco 1
MY - Malesia 1
PK - Pakistan 1
RS - Serbia 1
SA - Arabia Saudita 1
SK - Slovacchia (Repubblica Slovacca) 1
TH - Thailandia 1
TJ - Tagikistan 1
UY - Uruguay 1
UZ - Uzbekistan 1
VE - Venezuela 1
ZA - Sudafrica 1
Totale 11.955
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Città #
Southend 1.206
Chandler 1.009
Jacksonville 900
Woodbridge 727
Singapore 535
Ann Arbor 530
Dublin 347
Ashburn 285
Houston 239
Verona 172
Beijing 148
New York 147
Lawrence 143
Princeton 143
Helsinki 130
Wilmington 119
Nanjing 91
Jinan 83
Sindelfingen 77
Boardman 68
Brussels 64
Shenyang 64
Hong Kong 57
Hebei 56
Seoul 51
Milan 50
Santa Clara 50
Tianjin 41
Ningbo 33
Jiaxing 29
Changsha 28
Taizhou 28
Guangzhou 27
Nanchang 27
Zhengzhou 27
Haikou 26
Seattle 26
Dong Ket 23
Hangzhou 23
Las Pinas 23
Kent 22
Norwalk 22
Lomé 20
Taiyuan 20
Chicago 18
Los Angeles 18
Moscow 18
Falkenstein 17
Redwood City 16
San Francisco 15
Dallas 14
Jakarta 14
Chions 13
Fairfield 13
Lancaster 12
Lappeenranta 12
Toronto 12
Washington 11
Fuzhou 10
New Taipei 10
Castiglione delle Stiviere 9
Shanghai 9
Amsterdam 8
Bolzano 8
Bovolone 7
Columbus 7
London 7
Dongguan 6
Frankfurt am Main 6
Lanzhou 6
Nuremberg 6
Redmond 6
San Diego 6
Shenzhen 6
Tappahannock 6
Cambridge 5
Edinburgh 5
Ottawa 5
Taipei 5
Tallinn 5
Turin 5
Auburn Hills 4
Bonndorf 4
Castegnero 4
Fremont 4
Genoa 4
Nairobi 4
Nettuno 4
Pieve di Soligo 4
Sovizzo 4
Tel Aviv 4
Trento 4
Vienna 4
Warsaw 4
Wuhan 4
Xi'an 4
Barletta 3
Bath 3
Belo Horizonte 3
Bologna 3
Totale 8.364
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Nome #
Hardware Design and Simulation for Verification 161
Efficient Control-Flow Subgraph Matching for Detecting Hardware Trojans in RTL Models 140
A 1000X Speed Up for Properties Completeness Evaluation 131
A Formal Support for Homogeneous Simulation of Heterogeneous Embedded Systems 125
Automatic HDL Conversion and Abstraction Methodologies 117
Real-Time Multi-Person Identification and Tracking via HPE and IMU Data Fusion 113
A-TEAM: Automatic template-based assertion miner 113
On the Reuse of RTL assertions in Systemc TLM Verification 110
An EFSM-based Approach for Functional ATPG 106
Enabling dynamic assertion-based verification of embedded software through model-driven design 106
UNIVERCM: The UNIversal VERsatile Computational Model for Heterogeneous System Integration 106
A CLP-based Functional ATPG for Extended FSMs 105
An Error Simulation Based Approach to Measure Error Coverage of Formal Properties 104
On the Reuse of VHDL Modules into SystemC Design 102
A Verification Methodology for Reconfigurable Systems 102
HIFSuite: Tools for HDL Code Conversion and Manipulation 101
Functional Verification based on the EFSM Model 101
Redundant Functional Faults Reduction by Saboteur Synthesis 99
A Co-Simulation Methodology for HW/SW Validation and Performance Estimation 98
Functional Fault Coverage: the Chamber of Secrets or an Accurate Estimation of Gate-Level Coverage? 96
Laboratorio di Linux 95
On the Use of a High-Level Fault Model to Analyze Logical Consequence of Properties 95
Reusing RTL assertion checkers for verification of SystemC TLM models 95
Symbad: Formal Verification in System Level-based Design (Extended Version) 94
A SystemC-based Framework for Properties Incompleteness Evaluation 93
Dynamic and Formal Verification of Embedded Systems: A Comparative Survey 93
UNIVERCM: the UNIversal VERsatile Computational Model for heterogeneous embedded system design 93
Mixing ATPG and Property Checking for Testing HW/SW Interfaces 92
Effective EFSM generation for HW/SW-design verification 92
Combining Dynamic Slicing and Mutation Operators for ESL Correction 92
Symbad: Formal Verification in System Level-based Design 91
FATE: a Functional ATPG to Traverse unstabilized EFSMs 91
Automatic Abstraction of RTL IPs into Equivalent TLM Descriptions 91
Dynamic property mining for embedded software 91
Exploiting sub-graph isomorphism and probabilistic neural networks for the detection of hardware Trojans at RTL 90
A Timing-Accurate HW/SW Co-Simulation of an ISS with SystemC 89
On the Reuse of TLM Mutation Analysis at RTL 89
At-Speed Functional Verification of Programmable Devices 88
MOUSSE: scaling MOdelling and verification to complex heterogeneoUS embedded Systems Evolution 88
Improving High-Level and Gate-Level Testing with FATE: a Functional ATPG Traversing Unstabilized EFSMs 87
A Smooth Refinement Flow for Co-designing HW and SW Threads 87
A graph-based approach for mobile localization exploiting real and virtual landmarks 87
Mangrove: an Inference-based Dynamic Invariant Mining for GPU Architectures 87
AMLETO: A Multi-language Environment for Functional Test Generation 87
Hybrid Incremental Assertion-Based Verification for Functional Validation in TLM Design Flows 86
Automatic generation of self-adaptive transactors from PSL assertions 86
Mutation Analysis for SystemC Designs at TLM 85
Fault model qualification by assertion mining 85
HIFSuite: Tools for HDL Code Conversion and Manipulation 85
Logic-Level Analysis of High-Level Faults 84
Improving Gate-Level ATPG by Traversing Concurrent EFSMs 84
A testbench specification language for SystemC Verification 84
On the use of assertions for embedded-software dynamic verification 84
Testbench qualification of SystemC TLM protocols through Mutation Analysis 84
Semiformal Assertion-Based Verification of Hardware/Software Systems in a Model-Driven Design Framework 84
Automatic generation of power state machines through dynamic mining of temporal assertions 84
Automatic extraction of assertions from execution traces of behavioural models 83
Exploiting GPU Architectures for Dynamic Invariant Mining 83
On the Use of a High-level Fault Model to Check Properties Incompleteness 82
Coverage of Formal Properties based on a High-Level Fault Model and Functional ATPG 82
SystemC as a Complete Design and Validation Environment 82
EFSM Manipulation to Increase High-Level ATPG 81
A TLM Design for Verification Methodology 81
Functional Verification of Networked Embedded Systems 80
Test Generation: A Symbolic Approach 80
Towards a wearable system for predicting the freezing of gait in people affected by Parkinson's disease 80
A Methodology for Abstracting RTL Designs into TL Descriptions 79
Test generation based on CLP 79
Correct-by-construction generation of device drivers based on RTL testbenches 78
Time-Constraint-Aware Optimization of Assertions in Embedded Software 78
Automatic Generation of Compact Formal Properties for Effective Error Detection 78
The Strange Pair: IP-XACT and UNIVERCM to Integrate Heterogeneous Embedded Systems 78
Logic-Level Mapping of High-Level Faults 77
A Pseudo-Deterministic Functional ATPG based on EFSM Traversing 77
An Optimized CLP-based Technique for Generating Propagation Sequences 77
Redesign and Verification of RTL IPs through RTL-to-TLM Abstraction and TLM Synthesis 77
Optimization of assertion placement in time-constrained embedded systems 77
Accurate Profiling of Oracles for Self-Checking Time-Constrained Embedded Software 77
Simplified stimuli generation for scenario and assertion based verification 77
A time-window based approach for dynamic assertions mining on control signals 77
Automatic Generation and Qualification of Assertions on Control Signals: A Time Window-Based Approach 77
Automatic generation of EFSMs and HLDDs for functional ATPG 76
IPA: Reusing of Properties after Discretization of Hybrid Automata 76
RTL property abstraction for TLM assertion-based verification 76
Incremental ABV for TL-to-RTL Design Refinement 75
Vacuity Analysis by Fault Simulation 75
On the Use of a Fault Model to Validate the Completeness of a Set of Properties 74
Incremental ABV for Functional Validation of TL-to-RTL Design Refinement 74
The impact of EFSM composition on functional ATPG 74
IPA: Assertion-based verification in embedded-software design 74
On the Functional Qualification of a Platform Model 73
DDPSL: an Easy Way of Defining Properties 73
Model-Driven Design and Validation of Embedded Software 73
On the Evaluation of Transactor-based Verification for Reusing TLM Assertions and Testbenches at RTL 72
On the Co-simulation of SystemC with QEMU and OVP Virtual Platforms 72
Reuse and Optimization of Testbenches and Properties in a TLM-to-RTL Design Flow 71
Semi-Formal Functional Verification by EFSM traversing via NuSMV 71
Work-in-Progress: DOVE: Pinpointing firmware security vulnerabilities via symbolic control flow assertion mining 71
Too Few or too Many Properties? Measure it by ATPG! 70
A Mutation Model for the SystemC TLM 2.0 Communication Interfaces 70
Totale 8.795
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Categoria #
all - tutte 47.817
article - articoli 9.149
book - libri 252
conference - conferenze 35.670
curatela - curatele 0
other - altro 0
patent - brevetti 0
selected - selezionate 0
volume - volumi 2.746
Totale 95.634
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Totale Lug Ago Sett Ott Nov Dic Gen Feb Mar Apr Mag Giu
2019/2020513 0 0 0 0 0 0 108 93 47 119 32 114
2020/20211.156 70 185 38 122 145 156 34 99 115 20 109 63
2021/20221.156 68 326 12 112 77 22 19 53 48 35 98 286
2022/20232.790 197 275 269 465 286 568 52 191 337 54 66 30
2023/20241.470 75 118 123 151 110 281 105 95 27 117 196 72
2024/20251.580 173 341 113 592 129 176 56 0 0 0 0 0
Totale 12.220