CATALOGO DEI PRODOTTI DELLA RICERCA

PRAVADELLI, Graziano
 Distribuzione geografica
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Continente #
NA - Nord America 6.970
EU - Europa 4.820
AS - Asia 3.662
SA - Sud America 433
AF - Africa 64
OC - Oceania 17
Continente sconosciuto - Info sul continente non disponibili 6
Totale 15.972
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Nazione #
US - Stati Uniti d'America 6.892
GB - Regno Unito 1.433
SG - Singapore 1.423
CN - Cina 1.184
IT - Italia 628
HK - Hong Kong 552
SE - Svezia 485
FR - Francia 400
FI - Finlandia 399
RU - Federazione Russa 398
BR - Brasile 380
DE - Germania 374
IE - Irlanda 357
KR - Corea 152
VN - Vietnam 100
UA - Ucraina 95
BE - Belgio 64
CA - Canada 47
IN - India 37
NL - Olanda 37
PL - Polonia 35
ES - Italia 31
AT - Austria 30
TR - Turchia 29
PH - Filippine 25
JP - Giappone 22
BD - Bangladesh 21
MX - Messico 20
TG - Togo 20
TW - Taiwan 20
ID - Indonesia 16
AR - Argentina 14
ZA - Sudafrica 14
AU - Australia 11
IQ - Iraq 11
PE - Perù 11
IL - Israele 9
MA - Marocco 9
UZ - Uzbekistan 8
AE - Emirati Arabi Uniti 7
CL - Cile 7
SA - Arabia Saudita 7
EC - Ecuador 6
EG - Egitto 6
AZ - Azerbaigian 5
CO - Colombia 5
EE - Estonia 5
EU - Europa 5
JO - Giordania 5
KE - Kenya 5
NO - Norvegia 5
NZ - Nuova Zelanda 5
PK - Pakistan 5
AL - Albania 4
CH - Svizzera 4
CZ - Repubblica Ceca 4
KG - Kirghizistan 4
KZ - Kazakistan 4
NP - Nepal 4
PY - Paraguay 4
BG - Bulgaria 3
DK - Danimarca 3
DO - Repubblica Dominicana 3
IR - Iran 3
LT - Lituania 3
LU - Lussemburgo 3
LV - Lettonia 3
MD - Moldavia 3
PT - Portogallo 3
UY - Uruguay 3
VE - Venezuela 3
AM - Armenia 2
GR - Grecia 2
HU - Ungheria 2
RE - Reunion 2
RO - Romania 2
TJ - Tagikistan 2
TN - Tunisia 2
A2 - ???statistics.table.value.countryCode.A2??? 1
BB - Barbados 1
BF - Burkina Faso 1
BH - Bahrain 1
BN - Brunei Darussalam 1
BY - Bielorussia 1
DZ - Algeria 1
ET - Etiopia 1
GI - Gibilterra 1
GM - Gambi 1
GP - Guadalupe 1
GT - Guatemala 1
HN - Honduras 1
JM - Giamaica 1
LK - Sri Lanka 1
ML - Mali 1
MY - Malesia 1
NI - Nicaragua 1
PA - Panama 1
PW - Palau 1
RS - Serbia 1
SI - Slovenia 1
Totale 15.968
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Città #
Southend 1.206
Chandler 1.009
Jacksonville 901
Dallas 776
Singapore 730
Woodbridge 727
Hong Kong 541
Ann Arbor 530
Dublin 353
Ashburn 342
Houston 239
Verona 188
Beijing 164
New York 159
Lawrence 143
Princeton 143
Helsinki 132
Wilmington 119
The Dalles 109
Milan 107
Nanjing 92
Jinan 83
Los Angeles 82
Sindelfingen 77
Boardman 70
Brussels 64
Shenyang 64
Columbus 63
Santa Clara 62
Buffalo 61
Hebei 56
Seoul 51
Tianjin 41
São Paulo 38
Munich 34
Ningbo 33
Chicago 31
Changsha 29
Guangzhou 29
Jiaxing 29
Seattle 28
Taizhou 28
Haikou 27
Nanchang 27
San Francisco 27
Zhengzhou 27
Hangzhou 25
Warsaw 24
Dong Ket 23
Ho Chi Minh City 23
Las Pinas 23
Kent 22
Norwalk 22
Nuremberg 22
Lomé 20
Madrid 20
Taiyuan 20
Frankfurt am Main 18
Moscow 18
Toronto 18
Falkenstein 17
Lappeenranta 17
London 17
Tokyo 17
Vienna 17
Redwood City 16
Amsterdam 15
Redondo Beach 15
Fairfield 14
Hanoi 14
Jakarta 14
Stockholm 14
Chions 13
Brooklyn 12
Lancaster 12
Phoenix 12
Shanghai 12
Brasília 11
Rio de Janeiro 11
Turku 11
Washington 11
Belo Horizonte 10
Fuzhou 10
New Taipei 10
Rome 10
Castiglione delle Stiviere 9
Council Bluffs 9
Johannesburg 9
Mexico City 9
Montreal 9
Shenzhen 9
Ankara 8
Atlanta 8
Bolzano 8
Charlotte 8
Bovolone 7
Cambridge 7
Tashkent 7
Bologna 6
Boston 6
Totale 10.620
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Nome #
Hardware Design and Simulation for Verification 176
A Formal Support for Homogeneous Simulation of Heterogeneous Embedded Systems 171
A CLP-based Functional ATPG for Extended FSMs 167
A 1000X Speed Up for Properties Completeness Evaluation 163
Efficient Control-Flow Subgraph Matching for Detecting Hardware Trojans in RTL Models 157
A Co-Simulation Methodology for HW/SW Validation and Performance Estimation 146
Automatic HDL Conversion and Abstraction Methodologies 141
Enabling dynamic assertion-based verification of embedded software through model-driven design 132
A-TEAM: Automatic template-based assertion miner 132
Logic-Level Mapping of High-Level Faults 131
Real-Time Multi-Person Identification and Tracking via HPE and IMU Data Fusion 130
HIFSuite: Tools for HDL Code Conversion and Manipulation 126
UNIVERCM: the UNIversal VERsatile Computational Model for heterogeneous embedded system design 126
Functional Verification based on the EFSM Model 126
On the Reuse of RTL assertions in Systemc TLM Verification 126
An EFSM-based Approach for Functional ATPG 125
UNIVERCM: The UNIversal VERsatile Computational Model for Heterogeneous System Integration 125
Semiformal Assertion-Based Verification of Hardware/Software Systems in a Model-Driven Design Framework 123
Functional Fault Coverage: the Chamber of Secrets or an Accurate Estimation of Gate-Level Coverage? 122
A SystemC-based Framework for Properties Incompleteness Evaluation 121
On the Reuse of VHDL Modules into SystemC Design 120
Redundant Functional Faults Reduction by Saboteur Synthesis 120
Improving High-Level and Gate-Level Testing with FATE: a Functional ATPG Traversing Unstabilized EFSMs 119
Combining Dynamic Slicing and Mutation Operators for ESL Correction 119
Towards a wearable system for predicting the freezing of gait in people affected by Parkinson's disease 119
Effective EFSM generation for HW/SW-design verification 118
A Verification Methodology for Reconfigurable Systems 118
Symbad: Formal Verification in System Level-based Design (Extended Version) 117
An Error Simulation Based Approach to Measure Error Coverage of Formal Properties 116
A graph-based approach for mobile localization exploiting real and virtual landmarks 116
Mixing ATPG and Property Checking for Testing HW/SW Interfaces 114
On the Use of a High-Level Fault Model to Analyze Logical Consequence of Properties 114
Dynamic and Formal Verification of Embedded Systems: A Comparative Survey 114
A testbench specification language for SystemC Verification 114
Fault model qualification by assertion mining 114
FATE: a Functional ATPG to Traverse unstabilized EFSMs 113
A Smooth Refinement Flow for Co-designing HW and SW Threads 113
Mangrove: an Inference-based Dynamic Invariant Mining for GPU Architectures 113
EFSM Manipulation to Increase High-Level ATPG 112
A Methodology for Abstracting RTL Designs into TL Descriptions 111
Test generation based on CLP 111
A Timing-Accurate HW/SW Co-Simulation of an ISS with SystemC 110
A Pseudo-Deterministic Functional ATPG based on EFSM Traversing 110
Dynamic property mining for embedded software 109
Reusing RTL assertion checkers for verification of SystemC TLM models 109
Improving Gate-Level ATPG by Traversing Concurrent EFSMs 108
Mutation Analysis for SystemC Designs at TLM 108
On the Reuse of TLM Mutation Analysis at RTL 108
Symbad: Formal Verification in System Level-based Design 107
Automatic Abstraction of RTL IPs into Equivalent TLM Descriptions 107
Exploiting GPU Architectures for Dynamic Invariant Mining 107
HIFSuite: Tools for HDL Code Conversion and Manipulation 107
Laboratorio di Linux 106
MOUSSE: scaling MOdelling and verification to complex heterogeneoUS embedded Systems Evolution 105
Exploiting sub-graph isomorphism and probabilistic neural networks for the detection of hardware Trojans at RTL 105
Hybrid Incremental Assertion-Based Verification for Functional Validation in TLM Design Flows 104
Automatic generation of power state machines through dynamic mining of temporal assertions 104
Automatic generation of EFSMs and HLDDs for functional ATPG 103
On the use of assertions for embedded-software dynamic verification 103
Redesign and Verification of RTL IPs through RTL-to-TLM Abstraction and TLM Synthesis 102
AMLETO: A Multi-language Environment for Functional Test Generation 102
SystemC as a Complete Design and Validation Environment 101
DDPSL: an Easy Way of Defining Properties 101
Optimization of assertion placement in time-constrained embedded systems 101
Testbench qualification of SystemC TLM protocols through Mutation Analysis 101
Automatic generation of self-adaptive transactors from PSL assertions 101
Practical identity recognition using WiFi's Channel State Information 101
At-Speed Functional Verification of Programmable Devices 100
A Mutation Model for the SystemC TLM 2.0 Communication Interfaces 100
Automatic extraction of assertions from execution traces of behavioural models 100
On the Use of a High-level Fault Model to Check Properties Incompleteness 99
Correct-by-construction generation of device drivers based on RTL testbenches 99
Logic-Level Analysis of High-Level Faults 98
Test Generation: A Symbolic Approach 98
An Optimized CLP-based Technique for Generating Propagation Sequences 98
Accurate Profiling of Oracles for Self-Checking Time-Constrained Embedded Software 98
Vacuity Analysis by Fault Simulation 97
IPA: Reusing of Properties after Discretization of Hybrid Automata 97
RTOS-aware refinement for TLM2.0-based HW/SW designs 96
A time-window based approach for dynamic assertions mining on control signals 96
Automatic Generation and Qualification of Assertions on Control Signals: A Time Window-Based Approach 96
A virtual coaching platform to support therapy compliance in obesity 96
The impact of EFSM composition on functional ATPG 95
On the Functional Qualification of a Platform Model 95
Model-Driven Design and Validation of Embedded Software 95
Coverage of Formal Properties based on a High-Level Fault Model and Functional ATPG 94
A TLM Design for Verification Methodology 94
Automatic Generation of Compact Formal Properties for Effective Error Detection 94
Simplified stimuli generation for scenario and assertion based verification 94
Functional Verification of Networked Embedded Systems 93
A containerized ROS-compliant verification environment for robotic systems 93
IPA: Assertion-based verification in embedded-software design 92
Time-Constraint-Aware Optimization of Assertions in Embedded Software 92
A low-cost wireless body area network for human activity recognition in healthy life and medical applications 91
Incremental ABV for TL-to-RTL Design Refinement 91
On the Co-simulation of SystemC with QEMU and OVP Virtual Platforms 91
RTL property abstraction for TLM assertion-based verification 91
A low-cost BLE-based distance estimation, occupancy detection and counting system 91
On the Use of a Fault Model to Validate the Completeness of a Set of Properties 89
Semi-Formal Functional Verification by EFSM traversing via NuSMV 89
Totale 11.053
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Categoria #
all - tutte 63.729
article - articoli 12.752
book - libri 316
conference - conferenze 47.089
curatela - curatele 0
other - altro 0
patent - brevetti 0
selected - selezionate 0
volume - volumi 3.572
Totale 127.458
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Totale Lug Ago Sett Ott Nov Dic Gen Feb Mar Apr Mag Giu
2020/2021901 0 0 38 122 145 156 34 99 115 20 109 63
2021/20221.156 68 326 12 112 77 22 19 53 48 35 98 286
2022/20232.790 197 275 269 465 286 568 52 191 337 54 66 30
2023/20241.470 75 118 123 151 110 281 105 95 27 117 196 72
2024/20253.506 173 341 113 592 129 176 64 253 429 220 362 654
2025/20262.107 762 649 696 0 0 0 0 0 0 0 0 0
Totale 16.253