CATALOGO DEI PRODOTTI DELLA RICERCA

PRAVADELLI, Graziano
 Distribuzione geografica
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Continente #
NA - Nord America 5.287
EU - Europa 3.830
AS - Asia 1.265
OC - Oceania 15
SA - Sud America 10
Continente sconosciuto - Info sul continente non disponibili 6
AF - Africa 3
Totale 10.416
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Nazione #
US - Stati Uniti d'America 5.262
GB - Regno Unito 1.394
CN - Cina 901
SE - Svezia 473
IT - Italia 439
IE - Irlanda 349
FR - Francia 344
FI - Finlandia 313
DE - Germania 280
SG - Singapore 118
UA - Ucraina 90
BE - Belgio 59
HK - Hong Kong 58
KR - Corea 54
VN - Vietnam 42
PH - Filippine 23
RU - Federazione Russa 22
TW - Taiwan 19
CA - Canada 18
IN - India 17
NL - Olanda 17
TR - Turchia 12
AU - Australia 11
IL - Israele 8
MX - Messico 7
PL - Polonia 6
EU - Europa 5
JP - Giappone 5
CL - Cile 4
NO - Norvegia 4
NZ - Nuova Zelanda 4
AL - Albania 3
AT - Austria 3
CH - Svizzera 3
CZ - Repubblica Ceca 3
EE - Estonia 3
ES - Italia 3
LU - Lussemburgo 3
LV - Lettonia 3
MD - Moldavia 3
BG - Bulgaria 2
BR - Brasile 2
DK - Danimarca 2
GR - Grecia 2
PE - Perù 2
PT - Portogallo 2
RO - Romania 2
A2 - ???statistics.table.value.countryCode.A2??? 1
BN - Brunei Darussalam 1
CO - Colombia 1
EC - Ecuador 1
EG - Egitto 1
HU - Ungheria 1
IR - Iran 1
KG - Kirghizistan 1
KZ - Kazakistan 1
LK - Sri Lanka 1
MA - Marocco 1
MY - Malesia 1
RS - Serbia 1
SA - Arabia Saudita 1
SK - Slovacchia (Repubblica Slovacca) 1
TH - Thailandia 1
ZA - Sudafrica 1
Totale 10.416
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Città #
Southend 1.206
Chandler 1.009
Jacksonville 900
Woodbridge 727
Ann Arbor 530
Dublin 346
Houston 239
Ashburn 237
Verona 159
New York 147
Beijing 145
Lawrence 143
Princeton 143
Wilmington 119
Nanjing 91
Jinan 83
Singapore 79
Sindelfingen 77
Boardman 68
Helsinki 63
Shenyang 62
Brussels 59
Hebei 56
Hong Kong 51
Seoul 51
Milan 49
Tianjin 39
Ningbo 33
Jiaxing 29
Changsha 28
Taizhou 28
Nanchang 27
Haikou 26
Seattle 26
Zhengzhou 25
Dong Ket 23
Hangzhou 23
Las Pinas 23
Kent 22
Norwalk 22
Guangzhou 19
Taiyuan 19
Chicago 18
Redwood City 16
San Francisco 15
Los Angeles 14
Chions 13
Fairfield 13
Lancaster 12
Lappeenranta 11
Washington 11
Fuzhou 10
New Taipei 10
Castiglione delle Stiviere 9
Bolzano 8
Bovolone 7
Columbus 7
Toronto 7
Lanzhou 6
Moscow 6
Redmond 6
San Diego 6
Shanghai 6
Tappahannock 6
Cambridge 5
Dallas 5
Dongguan 5
Edinburgh 5
London 5
Taipei 5
Turin 5
Auburn Hills 4
Bonndorf 4
Castegnero 4
Fremont 4
Nettuno 4
Pieve di Soligo 4
Tel Aviv 4
Trento 4
Warsaw 4
Amsterdam 3
Barletta 3
Bath 3
Bologna 3
Brisbane 3
Clearwater 3
Conegliano 3
Duncan 3
Frankfurt am Main 3
Groningen 3
Livigno 3
Luxembourg 3
Melbourne 3
Nuremberg 3
Osnabrück 3
Ottawa 3
Paris 3
Riga 3
Saint-martin-d'heres 3
San Giovanni Lupatoto 3
Totale 7.599
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Nome #
Hardware Design and Simulation for Verification 155
Efficient Control-Flow Subgraph Matching for Detecting Hardware Trojans in RTL Models 132
A Formal Support for Homogeneous Simulation of Heterogeneous Embedded Systems 116
A 1000X Speed Up for Properties Completeness Evaluation 114
A-TEAM: Automatic template-based assertion miner 107
Automatic HDL Conversion and Abstraction Methodologies 101
Real-Time Multi-Person Identification and Tracking via HPE and IMU Data Fusion 99
An Error Simulation Based Approach to Measure Error Coverage of Formal Properties 99
Enabling dynamic assertion-based verification of embedded software through model-driven design 99
HIFSuite: Tools for HDL Code Conversion and Manipulation 97
An EFSM-based Approach for Functional ATPG 96
On the Reuse of RTL assertions in Systemc TLM Verification 96
UNIVERCM: The UNIversal VERsatile Computational Model for Heterogeneous System Integration 95
On the Reuse of VHDL Modules into SystemC Design 94
A Verification Methodology for Reconfigurable Systems 94
Functional Verification based on the EFSM Model 93
Laboratorio di Linux 90
Symbad: Formal Verification in System Level-based Design (Extended Version) 89
Redundant Functional Faults Reduction by Saboteur Synthesis 87
Functional Fault Coverage: the Chamber of Secrets or an Accurate Estimation of Gate-Level Coverage? 87
Dynamic and Formal Verification of Embedded Systems: A Comparative Survey 87
On the Use of a High-Level Fault Model to Analyze Logical Consequence of Properties 86
Reusing RTL assertion checkers for verification of SystemC TLM models 85
FATE: a Functional ATPG to Traverse unstabilized EFSMs 84
Effective EFSM generation for HW/SW-design verification 84
Automatic Abstraction of RTL IPs into Equivalent TLM Descriptions 84
UNIVERCM: the UNIversal VERsatile Computational Model for heterogeneous embedded system design 84
A SystemC-based Framework for Properties Incompleteness Evaluation 83
Mixing ATPG and Property Checking for Testing HW/SW Interfaces 82
Dynamic property mining for embedded software 82
Combining Dynamic Slicing and Mutation Operators for ESL Correction 81
On the Reuse of TLM Mutation Analysis at RTL 81
At-Speed Functional Verification of Programmable Devices 80
MOUSSE: scaling MOdelling and verification to complex heterogeneoUS embedded Systems Evolution 80
AMLETO: A Multi-language Environment for Functional Test Generation 80
Logic-Level Analysis of High-Level Faults 79
A Timing-Accurate HW/SW Co-Simulation of an ISS with SystemC 79
Fault model qualification by assertion mining 79
Exploiting sub-graph isomorphism and probabilistic neural networks for the detection of hardware Trojans at RTL 79
Mangrove: an Inference-based Dynamic Invariant Mining for GPU Architectures 78
Symbad: Formal Verification in System Level-based Design 77
Improving Gate-Level ATPG by Traversing Concurrent EFSMs 77
Hybrid Incremental Assertion-Based Verification for Functional Validation in TLM Design Flows 77
Automatic generation of self-adaptive transactors from PSL assertions 77
Improving High-Level and Gate-Level Testing with FATE: a Functional ATPG Traversing Unstabilized EFSMs 76
A CLP-based Functional ATPG for Extended FSMs 76
Mutation Analysis for SystemC Designs at TLM 76
HIFSuite: Tools for HDL Code Conversion and Manipulation 76
Functional Verification of Networked Embedded Systems 75
A TLM Design for Verification Methodology 75
On the use of assertions for embedded-software dynamic verification 75
Automatic extraction of assertions from execution traces of behavioural models 75
Exploiting GPU Architectures for Dynamic Invariant Mining 75
On the Use of a High-level Fault Model to Check Properties Incompleteness 74
Coverage of Formal Properties based on a High-Level Fault Model and Functional ATPG 74
SystemC as a Complete Design and Validation Environment 74
Correct-by-construction generation of device drivers based on RTL testbenches 74
A graph-based approach for mobile localization exploiting real and virtual landmarks 74
Time-Constraint-Aware Optimization of Assertions in Embedded Software 73
Testbench qualification of SystemC TLM protocols through Mutation Analysis 73
The Strange Pair: IP-XACT and UNIVERCM to Integrate Heterogeneous Embedded Systems 73
Automatic generation of power state machines through dynamic mining of temporal assertions 73
Test Generation: A Symbolic Approach 72
A Co-Simulation Methodology for HW/SW Validation and Performance Estimation 72
Redesign and Verification of RTL IPs through RTL-to-TLM Abstraction and TLM Synthesis 72
A testbench specification language for SystemC Verification 72
Semiformal Assertion-Based Verification of Hardware/Software Systems in a Model-Driven Design Framework 72
EFSM Manipulation to Increase High-Level ATPG 71
Incremental ABV for Functional Validation of TL-to-RTL Design Refinement 71
A Smooth Refinement Flow for Co-designing HW and SW Threads 71
Simplified stimuli generation for scenario and assertion based verification 71
RTL property abstraction for TLM assertion-based verification 71
Logic-Level Mapping of High-Level Faults 70
Automatic Generation of Compact Formal Properties for Effective Error Detection 70
On the Use of a Fault Model to Validate the Completeness of a Set of Properties 69
A Methodology for Abstracting RTL Designs into TL Descriptions 69
Reuse and Optimization of Testbenches and Properties in a TLM-to-RTL Design Flow 69
An Optimized CLP-based Technique for Generating Propagation Sequences 69
Automatic generation of EFSMs and HLDDs for functional ATPG 69
Optimization of assertion placement in time-constrained embedded systems 69
Automatic Generation and Qualification of Assertions on Control Signals: A Time Window-Based Approach 69
The impact of EFSM composition on functional ATPG 68
Semi-Formal Functional Verification by EFSM traversing via NuSMV 68
Accurate Profiling of Oracles for Self-Checking Time-Constrained Embedded Software 68
On the Evaluation of Transactor-based Verification for Reusing TLM Assertions and Testbenches at RTL 67
Incremental ABV for TL-to-RTL Design Refinement 67
Test generation based on CLP 67
A time-window based approach for dynamic assertions mining on control signals 67
A Pseudo-Deterministic Functional ATPG based on EFSM Traversing 66
RTOS-aware refinement for TLM2.0-based HW/SW designs 66
DDPSL: an Easy Way of Defining Properties 66
Vacuity Analysis by Fault Simulation 65
On the Functional Qualification of a Platform Model 65
Towards a wearable system for predicting the freezing of gait in people affected by Parkinson's disease 65
Too Few or too Many Properties? Measure it by ATPG! 64
Model-Driven Design and Validation of Embedded Software 64
IPA: Assertion-based verification in embedded-software design 64
The role of parallel simulation in functional verification 64
A Mutation Model for the SystemC TLM 2.0 Communication Interfaces 63
Vacuity Analysis for Property Qualification by Mutation of Checkers 63
Totale 7.911
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Categoria #
all - tutte 36.184
article - articoli 6.766
book - libri 200
conference - conferenze 27.064
curatela - curatele 0
other - altro 0
patent - brevetti 0
selected - selezionate 0
volume - volumi 2.154
Totale 72.368
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Totale Lug Ago Sett Ott Nov Dic Gen Feb Mar Apr Mag Giu
2019/20201.113 159 8 26 122 163 122 108 93 47 119 32 114
2020/20211.156 70 185 38 122 145 156 34 99 115 20 109 63
2021/20221.156 68 326 12 112 77 22 19 53 48 35 98 286
2022/20232.790 197 275 269 465 286 568 52 191 337 54 66 30
2023/20241.470 75 118 123 151 110 281 105 95 27 117 196 72
2024/202514 14 0 0 0 0 0 0 0 0 0 0 0
Totale 10.654