A Co-Simulation Methodology for HW/SW Validation and Performance Estimation

Co-simulation strategies allow to simulate and verify HW/SW embedded systems before the real platform is available. In this field, there is a large variety of approaches, that rely on different communication mechanisms to implement an efficient interface between the SW and the HW sim- ulators. However, the literature lacks a comprehensive methodology which addresses the need of integrating and synchronizing heterogeneous simulators, like for example the SystemC simulation kernel for HW modules and an instruction set simulator for SW applications, without being in- trusive for the HW and SW descriptions involved in the simulation. In this context, the paper presents, compares and integrates in a system-level framework two different co-simulation strate- gies for modeling, analyzing, and validating the performance of a HW/SW embedded system. Moreover, for both of them, a mechanism is proposed to provide an accurate time synchronization of the HW/SW communication. The first strategy is intended to provide an early co-simulation environment where HW/SW interaction can be validated without involving the operating system. The communication is implemented between a single SW task and a SystemC description of an HW module by exploiting the features of the remote debugging interface of a debugger (the GNU GDB), and by modifying the SystemC simulation kernel. On the contrary, the second strategy is intended to be used in further development steps, when the operating system is introduced to validate the co-simulation between HW modules and multitasking SW applications. In this approach, the communication is implemented via interrupts by using the features offered by the operating system.Experimental results are reported on two different case studies to analyze and compare the effectiveness of both the approaches.