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EnglishThe paper presents an automatic procedure for generating a particular kind of extended finite state machine, which allows a more uniform exploration of the state space of a design under verification. The proposed approach avoids the transition incompatibility problem which typically arises in actual HW/SW system descriptions. A EFSM-based ATPG, which exploits such a model, is able to more uniformly analyze the state space of the system with respect to using a generic EFSM.
| Titolo: | Effective EFSM generation for HW/SW-design verification |
| Autori: | |
| Data di pubblicazione: | 2010 |
| Abstract: | The paper presents an automatic procedure for generating a particular kind of extended finite state machine, which allows a more uniform exploration of the state space of a design under verification. The proposed approach avoids the transition incompatibility problem which typically arises in actual HW/SW system descriptions. A EFSM-based ATPG, which exploits such a model, is able to more uniformly analyze the state space of the system with respect to using a generic EFSM. |
| Handle: | http://hdl.handle.net/11562/345275 |
| ISBN: | 9781424473564 |
| Appare nelle tipologie: | 04.01 Contributo in atti di convegno |
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