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EnglishMany high-level fault models have been proposed in the past to perform verification at functional level, however high-level automatic test pattern generators (ATPGs) are still in a prototyping phase, while very efficient logic-level ATPGs are available. This paper proposes a strategy to map high-level faults into logic-level faults. Thus, functional verification, based on a high-level fault model, can be performed by exploiting the capability of state of the art logic-level ATPGs.
| Titolo: | Logic-Level Analysis of High-Level Faults | |
| Autori: | ||
| Data di pubblicazione: | 2004 | |
| Abstract: | Many high-level fault models have been proposed in the past to perform verification at functional level, however high-level automatic test pattern generators (ATPGs) are still in a prototyping phase, while very efficient logic-level ATPGs are available. This paper proposes a strategy to map high-level faults into logic-level faults. Thus, functional verification, based on a high-level fault model, can be performed by exploiting the capability of state of the art logic-level ATPGs. | |
| Handle: | http://hdl.handle.net/11562/16660 | |
| ISBN: | 1581138539 | |
| Appare nelle tipologie: | 04.01 Contributo in atti di convegno |
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