Automatic HDL Conversion and Abstraction Methodologies

Virtual prototyping of embedded systems generally relies on the reuse of already developed components to sensibly reduce the time-to-market. However, in several cases, manual rewriting of legacy components is necessary because their existing descriptions cannot be easily integrated in the new design. This may be due either to the use of a different description language, e.g., SystemC instead of VHDL, or to the adoption of a different abstraction layer, e.g., Transaction Level Modeling (TLM) instead of Register Transfer Level (RTL). Several co-simulation techniques and tools have been proposed and commercialized to solve such a problem, but it requires the set up of a complex environment to manage the simulation of heterogeneous components. Moreover, these solutions cannot guarantee an efficient correct-by- evolution development process, where, for example, the alignment between RTL and TLM descriptions of the same component must be preserved during the initial design and the further evolution of the product. In this context the paper presents the basic methodologies on which HIFSuite relies, a set of tools and APIs that allow system designers to automatize the reuse of existing components by providing conversion and abstraction capabilities, as well as easy development of custom tools for the automatic manipulation of HDL descriptions. In particular, HIFSuite allows to: (1) parse VHDL/Verilog RTL models; (2) extract an internal HIF representation; (3) manipulate the HIF representation through a set of powerful APIs; (4) abstract the HIF representation towards TLM; (5) generate an RTL or TLM 2.0 SystemC model which either reflects the changes introduced by steps 3 and/or 4, or it is functionally equivalent to the original VHDL/Verilog model.