Transaction Level Modeling (TLM) is becoming an usual practice for simplifying system-level design and architecture exploration. Nevertheless, different problems arise when designers attempt to fully exploit the features of a TLM-based design flow. Transactors generation and RTL IP-cores abstraction, for example, can heavily affect the verification quality as they are manually accomplished by designers. This work presents a methodology that aims at reaching two goals: (i) to define a design for verification approach that is a guideline to automatize some parts of design implementation to make easier the subsequent verification phases and (ii) to combine static and dynamic techniques in order to improve the verification quality.
A TLM Design for Verification Methodology
BOMBIERI, Nicola;FUMMI, Franco;PRAVADELLI, Graziano
2006-01-01
Abstract
Transaction Level Modeling (TLM) is becoming an usual practice for simplifying system-level design and architecture exploration. Nevertheless, different problems arise when designers attempt to fully exploit the features of a TLM-based design flow. Transactors generation and RTL IP-cores abstraction, for example, can heavily affect the verification quality as they are manually accomplished by designers. This work presents a methodology that aims at reaching two goals: (i) to define a design for verification approach that is a guideline to automatize some parts of design implementation to make easier the subsequent verification phases and (ii) to combine static and dynamic techniques in order to improve the verification quality.I documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.