The arising complexity of modern system-on-chips (SoCs) makes the reuse of existent IP cores a key strategy to explore these systems design space in a reasonable amount of time and to reduce the error risk during the design flow. On the other hand, although several RTL IPs are available to designers, their reuse throughout the design space exploration involves time consuming and error prone redesign steps (i.e., RTL redesign), which often eludes the IP reuse advantages. In this context, this paper proposes a methodology to automatically redesign RTL IPs when a system level description of such IPs (i.e., C/C++ model) is not available. The redesign methodology relies on an RTL-to-TLM abstraction step to abstract all the low level details related to the starting RTL model, and on a TLM synthesis step to generate the new RTL description. The methodology includes a verification phase to verify, by means of model checking, the correctness of each step of the redesign flow.

Redesign and Verification of RTL IPs through RTL-to-TLM Abstraction and TLM Synthesis

BOMBIERI, Nicola;FUMMI, Franco;GUARNIERI, Valerio;PRAVADELLI, Graziano;VINCO, Sara
2012

Abstract

The arising complexity of modern system-on-chips (SoCs) makes the reuse of existent IP cores a key strategy to explore these systems design space in a reasonable amount of time and to reduce the error risk during the design flow. On the other hand, although several RTL IPs are available to designers, their reuse throughout the design space exploration involves time consuming and error prone redesign steps (i.e., RTL redesign), which often eludes the IP reuse advantages. In this context, this paper proposes a methodology to automatically redesign RTL IPs when a system level description of such IPs (i.e., C/C++ model) is not available. The redesign methodology relies on an RTL-to-TLM abstraction step to abstract all the low level details related to the starting RTL model, and on a TLM synthesis step to generate the new RTL description. The methodology includes a verification phase to verify, by means of model checking, the correctness of each step of the redesign flow.
9780769548777
TLM synthesis; RTL-to-TLM abstraction; RTL redesign
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11562/345642
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