In transaction-level modeling (TLM), verification methodologies based on transactions allow test- benches, properties, and IP cores in mixed TL-RTL designs to be reused. However, no papers in the literature analyze the effectiveness of transaction-based verification (TBV) in comparison to the more traditional RTL approach. The first contribution of this article is the introduction of a functional-fault-model-based methodology for demonstrating the effectiveness of reuse through TBV. A second contribution is the introduction of a similar methodology for efficient property checking which identifies and removes redundant properties prior to assertion-based verification or model checking.
Titolo: | Reuse and Optimization of Testbenches and Properties in a TLM-to-RTL Design Flow |
Autori: | |
Data di pubblicazione: | 2008 |
Rivista: | |
Abstract: | In transaction-level modeling (TLM), verification methodologies based on transactions allow test- benches, properties, and IP cores in mixed TL-RTL designs to be reused. However, no papers in the literature analyze the effectiveness of transaction-based verification (TBV) in comparison to the more traditional RTL approach. The first contribution of this article is the introduction of a functional-fault-model-based methodology for demonstrating the effectiveness of reuse through TBV. A second contribution is the introduction of a similar methodology for efficient property checking which identifies and removes redundant properties prior to assertion-based verification or model checking. |
Handle: | http://hdl.handle.net/11562/321589 |
Appare nelle tipologie: | 01.01 Articolo in Rivista |