n the hardware design, assertion-based verification (ABV) affirmed as an effective methodology for functional verification, i.e., design specification conformance. However, up to now, there were only limited studies concerning the application of simulation-based ABV to embedded-software design and verification flow. We propose an analysis aiming to bridge such a gap. In particular, we illustrate how ABV can integrate and improve the various stages of the verification flow. Moreover, the analysis leads us to develop a comprehensive and practical dynamic ABV environment for micro-controller embedded-software.

IPA: Assertion-based verification in embedded-software design

DI GUGLIELMO, Giuseppe;DI GUGLIELMO, Luigi;FUMMI, Franco;PRAVADELLI, Graziano
2011-01-01

Abstract

n the hardware design, assertion-based verification (ABV) affirmed as an effective methodology for functional verification, i.e., design specification conformance. However, up to now, there were only limited studies concerning the application of simulation-based ABV to embedded-software design and verification flow. We propose an analysis aiming to bridge such a gap. In particular, we illustrate how ABV can integrate and improve the various stages of the verification flow. Moreover, the analysis leads us to develop a comprehensive and practical dynamic ABV environment for micro-controller embedded-software.
2011
9781457717444
Assertion-based verification; embedded software; V-model
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11562/373430
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