The development of more and more complex embedded systems constitutes a very challenging task for EDA experts, due to their HW/SW-mixed nature joint to the high demande for quality and reliability. Recently, both industrial engineers and accademic researchers have developed a very large of techniques for dynamic verification in terms of co-simulation. which, in particular, address the different nature of hardware and software components of an embedded system. However, a widely accepted methodology does not exist. Thus, this papers is intended to provide a general view on simulation-based modeling and verification strategy for developing embedded systems. In particular, the paper is focussed on describing state-of-the art co-simulation approaches and verification strategies based on fault simulation and assertion checking.

Hardware Design and Simulation for Verification

BOMBIERI, Nicola;FUMMI, Franco;PRAVADELLI, Graziano
2006-01-01

Abstract

The development of more and more complex embedded systems constitutes a very challenging task for EDA experts, due to their HW/SW-mixed nature joint to the high demande for quality and reliability. Recently, both industrial engineers and accademic researchers have developed a very large of techniques for dynamic verification in terms of co-simulation. which, in particular, address the different nature of hardware and software components of an embedded system. However, a widely accepted methodology does not exist. Thus, this papers is intended to provide a general view on simulation-based modeling and verification strategy for developing embedded systems. In particular, the paper is focussed on describing state-of-the art co-simulation approaches and verification strategies based on fault simulation and assertion checking.
3540343040
9783540343042
simulation; Verification
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11562/30670
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