More and more functional verification is attracting EDA researchers and industrial companies interested in digital system validation. Coverage metrics and functional fault models are used to guide the generation of functional tests achieving high fault coverage in a relatively short time with respect to traditional gate-level ATPGs. However, what is the effectiveness of test sequences generated at functional level with respect to the more traditional gate-level stuck at fault model? The paper presents an accurate analysis of the correlation between the high-level bit coverage fault model and the gate-level stuck-at fault model.

Functional Fault Coverage: the Chamber of Secrets or an Accurate Estimation of Gate-Level Coverage?

FUMMI, Franco;MARCONCINI, Cristina;PRAVADELLI, Graziano
2004

Abstract

More and more functional verification is attracting EDA researchers and industrial companies interested in digital system validation. Coverage metrics and functional fault models are used to guide the generation of functional tests achieving high fault coverage in a relatively short time with respect to traditional gate-level ATPGs. However, what is the effectiveness of test sequences generated at functional level with respect to the more traditional gate-level stuck at fault model? The paper presents an accurate analysis of the correlation between the high-level bit coverage fault model and the gate-level stuck-at fault model.
0769521193
Fault Model; ATPG
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Utilizza questo identificativo per citare o creare un link a questo documento: http://hdl.handle.net/11562/18110
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