CATALOGO DEI PRODOTTI DELLA RICERCA

FUMMI, Franco
 Distribuzione geografica
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Continente #
NA - Nord America 11.115
EU - Europa 9.052
AS - Asia 2.746
OC - Oceania 27
SA - Sud America 22
AF - Africa 7
Continente sconosciuto - Info sul continente non disponibili 7
Totale 22.976
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Nazione #
US - Stati Uniti d'America 11.064
GB - Regno Unito 3.163
CN - Cina 2.003
SE - Svezia 1.063
IT - Italia 872
IE - Irlanda 780
FR - Francia 758
FI - Finlandia 691
DE - Germania 606
RU - Federazione Russa 586
SG - Singapore 388
UA - Ucraina 220
KR - Corea 150
BE - Belgio 131
VN - Vietnam 69
JP - Giappone 54
CA - Canada 42
NL - Olanda 39
AU - Australia 22
ES - Italia 18
TR - Turchia 17
IN - India 16
AT - Austria 14
CZ - Repubblica Ceca 14
HK - Hong Kong 14
GR - Grecia 12
PL - Polonia 11
IL - Israele 10
BG - Bulgaria 9
DK - Danimarca 9
LV - Lettonia 9
EE - Estonia 8
MX - Messico 7
RO - Romania 7
BR - Brasile 6
AL - Albania 5
CL - Cile 5
LU - Lussemburgo 5
NZ - Nuova Zelanda 5
CO - Colombia 4
EU - Europa 4
HU - Ungheria 4
SA - Arabia Saudita 4
A2 - ???statistics.table.value.countryCode.A2??? 3
CH - Svizzera 3
ID - Indonesia 3
RS - Serbia 3
AE - Emirati Arabi Uniti 2
AR - Argentina 2
BO - Bolivia 2
HR - Croazia 2
KZ - Kazakistan 2
LK - Sri Lanka 2
MA - Marocco 2
MO - Macao, regione amministrativa speciale della Cina 2
NO - Norvegia 2
PE - Perù 2
PH - Filippine 2
SK - Slovacchia (Repubblica Slovacca) 2
TH - Thailandia 2
AZ - Azerbaigian 1
BN - Brunei Darussalam 1
BY - Bielorussia 1
CR - Costa Rica 1
EC - Ecuador 1
EG - Egitto 1
ET - Etiopia 1
IM - Isola di Man 1
IS - Islanda 1
KG - Kirghizistan 1
KW - Kuwait 1
LI - Liechtenstein 1
MD - Moldavia 1
NG - Nigeria 1
PA - Panama 1
PK - Pakistan 1
SC - Seychelles 1
SI - Slovenia 1
TW - Taiwan 1
ZA - Sudafrica 1
Totale 22.976
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Città #
Southend 2.814
Chandler 2.184
Jacksonville 1.959
Woodbridge 1.317
Ann Arbor 1.109
Dublin 768
Houston 705
Ashburn 627
Verona 379
Beijing 344
Lawrence 293
Princeton 293
Singapore 275
Wilmington 258
Nanjing 219
Jinan 194
Helsinki 174
Sindelfingen 156
Seoul 143
New York 138
Shenyang 135
Brussels 131
Boardman 121
Hebei 113
Tianjin 81
Nanchang 78
Jiaxing 73
Milan 72
Changsha 71
Ningbo 61
Washington 60
Zhengzhou 59
Taizhou 58
Haikou 55
Norwalk 51
Lancaster 49
Guangzhou 48
Seattle 46
Taiyuan 43
Hangzhou 41
Dong Ket 40
Tokyo 38
Fuzhou 30
Kent 29
San Francisco 24
Los Angeles 23
Fairfield 22
Naples 21
Redwood City 21
Lanzhou 20
Toronto 20
Chions 18
Chicago 16
Auburn Hills 15
Edinburgh 15
Lappeenranta 15
Champaign 14
Moscow 14
Falls Church 13
Tappahannock 13
Clearwater 12
Dallas 12
Stockholm 12
Trento 12
Rome 11
Frankfurt am Main 10
Santa Clara 10
Shanghai 10
San Diego 9
Vienna 9
Padova 8
Prague 8
Riva 8
Tallinn 8
Cassano 7
Melbourne 7
Munich 7
Newark 7
Torino 7
Turin 7
Amsterdam 6
Athens 6
Columbus 6
Dongguan 6
Dronten 6
Groningen 6
Ottawa 6
Paris 6
Sofia 6
Warsaw 6
Xi'an 6
Bonndorf 5
Boydton 5
Copenhagen 5
Donostia / San Sebastian 5
Falkenstein 5
Kemerovo 5
London 5
Mehlingen 5
Altavilla Silentina 4
Totale 16.507
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Nome #
Hardware Design and Simulation for Verification 157
Estimation of BUS Performance for a Tuplespace in an Embedded Architecture 127
A 1000X Speed Up for Properties Completeness Evaluation 118
A Formal Support for Homogeneous Simulation of Heterogeneous Embedded Systems 118
Code Generation Alternatives to Reduce Heterogeneous Embedded Systems to Homogeneity 115
A Combined Approach to Validate the Design of Embedded Network Devices 114
Modeling Network Embedded Systems with NS-2 and SystemC 113
Modelling, Simulation, and Tuning of Metabolic Networks Through Electronic Design Automation 113
Virtual Hardware Prototyping Through Timed Hardware-Software Co-Simulation 110
A SystemC-based Platform for Assertion-based Verification and Mutation Analysis in Systems Biology 110
HDTLib: an efficient implementation of SystemC data types for fast simulation at different abstraction levels 109
On the Reuse of Heterogeneous IPs into SysML Models for Integration Validation 109
On the reuse of RTL IPs for SysML model generation 108
Model-Driven Design for the Development of Multi-Platform Smartphone Applications 108
Integration of mixed-signal components into virtual platforms for holistic simulation of smart systems 108
Automatic HDL Conversion and Abstraction Methodologies 103
Combining Symbolic and Genetic Techniques for Efficient Sequential Circuit Test Generation 102
On the Automatic Generation of GPU‐oriented Software Applications from RTL IPs 102
An Improved Electronic Design Automation Methodology for modelling Leukocyte Integrin Activation 102
Automatic Integration of Cycle-accurate Descriptions with Continuous-time Models for Cyber-Physical Virtual Platforms 102
Native ISS-SystemC Integration for the Co-Simulation of Multi-Processor SoC 101
A WEB-CAD Methodology for IP-Core Analysis and Simulation 100
Heterogeneous Co-Simulation of Networked Embedded Systems 100
An Error Simulation Based Approach to Measure Error Coverage of Formal Properties 100
Analog Models Manipulation for Effective Integration in Smart System Virtual Platforms 100
Functional Design for Testability of Control-Dominated Architectures 99
An EFSM-based Approach for Functional ATPG 99
Enabling dynamic assertion-based verification of embedded software through model-driven design 99
On the Reuse of RTL assertions in Systemc TLM Verification 98
HIFSuite: Tools for HDL Code Conversion and Manipulation 97
UNIVERCM: The UNIversal VERsatile Computational Model for Heterogeneous System Integration 97
A SystemC-based framework for modeling and simulation of networked embedded systems 97
Dynamic modeling and simulation of leukocyte integrin activation through an electronic design automation framework 96
A Verification Methodology for Reconfigurable Systems 96
An Application of Genetic Algorithms and BDDs to Functional Testing 95
Automatic Network Protocol Synthesis from UML Sequence Diagrams 95
Functional Verification based on the EFSM Model 95
On the Reuse of VHDL Modules into SystemC Design 94
Power Characterization of LFSRs 94
A Complete Testing Strategy Based on Interacting and Hierarchical FSMs 94
Homogeneous Simulation: the Effective Integration Solution for Smart Systems 94
SystemC: A Homogenous Environment to Test Embedded Systems 92
Software/Network Co-Simulation of Heterogeneous Industrial Networks Architectures 92
Refinement of UML/MARTE models for the design of networked embedded systems 92
Increase the Behavioral Fault Model Accuracy Using High-level Synthesis Information 91
Legacy SystemC Co-Simulation of Multi-Processor Systems-on-Chip 91
Redundant Functional Faults Reduction by Saboteur Synthesis 91
Symbad: Formal Verification in System Level-based Design (Extended Version) 91
On the Use of a High-Level Fault Model to Analyze Logical Consequence of Properties 90
A Toolchain for UML-based Modeling and Simulation of Networked Embedded Systems 89
Testability Alternatives Exploration through Functional Testing 88
Symbolic Optimization of FSM Networks Based on Redundancies Identification and Removal 88
Functional Fault Coverage: the Chamber of Secrets or an Accurate Estimation of Gate-Level Coverage? 88
A Middleware-Centric Design Flow for Networked Embedded Systems 88
Reduced-Complexity Transition-Fault Test Generation for Non-Scan Circuits through High-level Mutant Injection 88
A SystemC Platform for Signal Transduction Modelling and Simulation in Systems Biology 88
Automatic abstraction of multi-discipline analog models for efficient functional simulation 88
A Timing-Accurate Modeling and Simulation Environment for Networked Embedded Systems 87
Two-Dimensional Sequential Array Architectures: Design for Testability and Reconfiguration Issues 87
Generation of SystemC/TLM code from UML/MARTE sequence diagrams for verification 87
Model-Driven Design of Network Aspects of Distributed Embedded Systems 87
Analog fault testing through abstraction 87
Efficient Implementation and Abstraction of SystemC Data Types for Fast Simulation 87
A VHDL Error Simulator for Functional Test Generation 86
An Energy-Aware Co-Simulation Framework for the Design of Wireless Sensor Networks 86
Communication-aware design flow for dependable networked embedded systems 86
Generation of VHDL code from UML/MARTE sequence diagrams for verification and synthesis 86
Cyber-physical Systems Integration in a Production Line Simulator 86
Mixing ATPG and Property Checking for Testing HW/SW Interfaces 85
A SystemC-based Framework for Properties Incompleteness Evaluation 85
FATE: a Functional ATPG to Traverse unstabilized EFSMs 85
Automatic Abstraction of RTL IPs into Equivalent TLM Descriptions 85
UNIVERCM: the UNIversal VERsatile Computational Model for heterogeneous embedded system design 85
Dynamic property mining for embedded software 85
Communication Alternatives Exploration in Model-Driven Design of Networked Embedded Systems 85
UML-based Modeling and Simulation of Environmental Effects in Networked Embedded Systems 85
Code Generation Alternatives to Reduce Heterogeneous Embedded Systems to Homogeneity 85
Reusing RTL assertion checkers for verification of SystemC TLM models 85
Controller and Data-Path Separation by VHDL Restructuring 84
Testability Analysis and Behavioral Testing of the Hopfield Neural Paradigm 84
Effective EFSM generation for HW/SW-design verification 84
On the Reuse of TLM Mutation Analysis at RTL 84
Modeling and Analysis of Heterogeneous Industrial Networks Architectures 84
Modeling in Industry 5.0: What Is There and What Is Missing: Special Session 1: Languages for Industry 5.0 84
AME: an Abstract Middleware Environment for Validating Networked Embedded Systems Applications 83
Combining Dynamic Slicing and Mutation Operators for ESL Correction 83
A Protected IP-Core Test Generation 82
Virtual in-circuit emulation for timing accurate system prototyping 82
Genetic Algorithms: the Philosopher’s Stone or an Effective Solution for High-Level TPG? 82
A Timing-Accurate HW/SW Co-Simulation of an ISS with SystemC 82
Hybrid Incremental Assertion-Based Verification for Functional Validation in TLM Design Flows 82
At-Speed Functional Verification of Programmable Devices 82
Synthesis for Testability of Highly Complex Controllers by Functional Redundancy Removal 82
Automatic Generation of Error Control Codes for Computer Applications 82
Mixing simulated and actual hardware devices to validate device drivers in a complex embedded platform 82
MOUSSE: scaling MOdelling and verification to complex heterogeneoUS embedded Systems Evolution 82
Integrating RTL IPs into TLM Designs Through Automatic Transactor Generation 82
On the Use of GP-GPUs for Accelerating Compute-intensive EDA Applications 82
An Enhanced Profiling Framework for the Analysis and Development of Parallel Primitives for GPUs 82
MIPP: A Microbenchmark Suite for Performance, Power, and Energy Consumption Characterization of GPU architectures 82
Totale 9.343
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Categoria #
all - tutte 78.530
article - articoli 14.338
book - libri 443
conference - conferenze 60.455
curatela - curatele 0
other - altro 0
patent - brevetti 0
selected - selezionate 0
volume - volumi 3.294
Totale 157.060
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Totale Lug Ago Sett Ott Nov Dic Gen Feb Mar Apr Mag Giu
2019/20202.058 0 12 28 276 268 304 229 193 96 256 102 294
2020/20212.536 182 422 92 287 314 363 45 200 194 38 272 127
2021/20222.690 169 790 18 194 329 81 46 107 72 80 202 602
2022/20236.003 409 638 563 1.041 570 1.222 84 377 654 203 173 69
2023/20243.042 156 241 333 361 376 431 140 193 45 200 393 173
2024/2025689 388 301 0 0 0 0 0 0 0 0 0 0
Totale 23.543