Verification of real time embedded systems is becoming more and more complex in terms of maintaining the code size and keeping equivalence between the specification. It requires the simulation of the system and the checking of its timing and functional properties as well as constraints. The paper presents a methodology which starts from UML sequence diagrams with MARTE timing constraints and generates a VHDL model with checkers. The simulation of the model allows to verify the specified sequence of exchanged information between components while checkers allow to verify that properties and timing constraints are met. The application of the methodology to the design of a wireless sensor node shows the validity of the approach and its simulation overhead.
Generation of VHDL code from UML/MARTE sequence diagrams for verification and synthesis
Ebeid, Emad Samuel Malki;QUAGLIA, Davide;FUMMI, Franco
2012
Abstract
Verification of real time embedded systems is becoming more and more complex in terms of maintaining the code size and keeping equivalence between the specification. It requires the simulation of the system and the checking of its timing and functional properties as well as constraints. The paper presents a methodology which starts from UML sequence diagrams with MARTE timing constraints and generates a VHDL model with checkers. The simulation of the model allows to verify the specified sequence of exchanged information between components while checkers allow to verify that properties and timing constraints are met. The application of the methodology to the design of a wireless sensor node shows the validity of the approach and its simulation overhead.
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