On the reuse of RTL IPs for SysML model generation

Model-based design is getting more and more consensus in the today embedded system design flows. In this context, SysML is becoming the de-facto reference modeling language as it allows designers to model a whole system, both HW and SW, at high levels of abstraction. The SysML description can be defined with different levels of detail, each one suitable to the design and functional verification requirements. In this paper, we propose a methodology for abstracting existing RTL IPs into SysML components. During the abstraction flow, it is possible to set the level of detail to be maintained in SysML, such as, hierarchical structure and data types of the IPs. However, the generated SysML models are complete of both structural and behavioral descriptions and, thus, they can be synthesized into C++, SystemC, or Java executable code for simulation by any commercial tool. As a consequence, the methodology relieves designers from the modeling time and error risks especially for those design and functional verification phases in which the SysML model of the HW architecture is particularly structured and detailed.