Today's embedded systems include more and more network capabilities. Verifying these capabilities via simulation is difficult because it is often required to have the simulation models interact with real networks. For instance, the validation of a network device requires its connection with the model of a real network and testing of its interaction with the surrounding blocks and used protocols. This paper explores a methodology for modeling, simulating and testing the functionality of an embedded system, and its interaction with a network. The methodology joins two simulation environments, both based on the C++ programming language. The first (SystemC) is both a hardware definition language and a simulation library designed to model and simulate hardware and software systems. The second (Network Simulator-2) is both a network definition language and a simulation tool designed to model and simulate network topologies. The proposed modeling and simulation methodology has been applied to two case studies: the design of a network device and the verification of two cooperating embedded systems.
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