A HW/SW co-simulation framework for the verification of multi-CPU systems

This work focuses on the HW/SW co-simulation of complex systems consisting of several independent CPU's (multi-CPU systems) such as multi-processor system-on-chip (MPSoC) and wireless sensor networks. The verification of such systems requires the efficient evaluation of hardware-software interactions in several processing units. We present a HW/SW co-simulation framework consisting of a timing-accurate interaction of a SystemC simulator with an array of instruction set simulators (ISS). Tests with up to one hundred ISS's show that the proposed framework exploits the power of today's multi-processor hosts and represents a valuable tool for the validation of not only eight-core MPSoC's but also large sensor networks.