Verification of cyber-physical systems SW often requires simulation of accurate heterogeneous HW models. However, heterogeneous system simulators do not easily allow it and designers must connect multiple simulators in complex co-simulation environments. Furthermore, usually HW computing platforms are “approximated” by using abstracted models that do not accurately reproduce the cycle-based execution of HW components. In this chapter we present the automatic generation of cycle-accurate Simulink blocks from the most popular HW description languages: VHDL and Verilog. The methodology starts from an IP core modeled in one of the two supported HW description languages. Then, it relies on state-of-the-art RTL models abstraction method to generate a functionally equivalent cycle-accurate model of the IP. Then, it uses two alternative mapping and code-generation techniques. The first relying on the portable FMI standard, while the other one exploits Mathworks’ proprietary C MEX S-Functions. These blocks can be easily integrated within Simulink to simulate digital HW components while avoiding to build complex co-simulation environments. A set of IP cores are used to evaluate the proposed approach. Furthermore, the experiments presented in this chapter compares the two proposed mapping and code-generation alternatives to highlight their advantages and drawbacks.

Automatic Integration of HDL IPs in Simulink Using FMI and S-Function Interfaces

stefano centomo
;
Michele Lora
;
Antonio Portaluri
;
Francesco Stefanni
;
Franco Fummi
2018

Abstract

Verification of cyber-physical systems SW often requires simulation of accurate heterogeneous HW models. However, heterogeneous system simulators do not easily allow it and designers must connect multiple simulators in complex co-simulation environments. Furthermore, usually HW computing platforms are “approximated” by using abstracted models that do not accurately reproduce the cycle-based execution of HW components. In this chapter we present the automatic generation of cycle-accurate Simulink blocks from the most popular HW description languages: VHDL and Verilog. The methodology starts from an IP core modeled in one of the two supported HW description languages. Then, it relies on state-of-the-art RTL models abstraction method to generate a functionally equivalent cycle-accurate model of the IP. Then, it uses two alternative mapping and code-generation techniques. The first relying on the portable FMI standard, while the other one exploits Mathworks’ proprietary C MEX S-Functions. These blocks can be easily integrated within Simulink to simulate digital HW components while avoiding to build complex co-simulation environments. A set of IP cores are used to evaluate the proposed approach. Furthermore, the experiments presented in this chapter compares the two proposed mapping and code-generation alternatives to highlight their advantages and drawbacks.
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Utilizza questo identificativo per citare o creare un link a questo documento: http://hdl.handle.net/11562/994731
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