Timed automata and timed finite state machins (TFSMs) have been proposed to represent more accurately the behaviour of systems in continuous time. Recently, we introduced a model of TFSMs that extends the expressive power of FSMs by introducing a single clock, timed guards which restrict when the input/output transitions may happen, and timeouts on the transitions. We derived an abstraction procedure to convert a TFSM into an equivalent untimed FSM. Here, we extend the model with output timeouts and derive a minimal form for deterministic TFSMs that reduces the number of states, the number of transitions and the timeout values at each state.
|Titolo:||Minimizing Deterministic Timed Finite State Machines|
VILLA, Tiziano (Corresponding)
|Data di pubblicazione:||2018|
|Appare nelle tipologie:||04.01 Contributo in atti di convegno|