This paper presents a methodology to produce synthesizable HW descriptions starting from UML State Machine based representations. This problem has already been widely addressed in the past. However, all the previously proposed approaches present a common characteristic: they restrict the expressiveness of the starting model. In particular, a common approach consists on the definition of ad-hoc UML profiles to adapt UML to the typical constructs of the classical hardware description languages. Thus, forcing the designer to use only a subset of the UML modeling language. This differentiates the initial UML model for SW and HW design, thus contradicting the main assumption of Model-Based design and avoiding code reuse. This paper aims at overcoming this limitation, by allowing the designer to use the same models for SW and HW design. To achieve this result, the UML description is mapped into a general purpose Model of Computation, called univer CM, to remove any ambiguity of the UML definition. After the application of some manipulations, the automata composing the univer CM models are translated into VHDL processes respecting the templates defined for the HW synthesis. The proposed approach has been validated on some commercial designs.
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