Transaction Level Modeling (TLM) is an emerging design practice forovercoming increasing design complexity. It aims at simplifying thedesign flow of embedded systems by designing and verifying a systemat different abstraction levels. In this context, transactors play afundamental role since they allow communication between the systemcomponents, implemented at different abstraction levels. Reuse ofRTL IPs into TLM systems is a meaningful example of key advantageguaranteed by exploiting transactors. Nevertheless, transactorsimplementation is still manual, tedious and error-prone, and the effortspent to verify their correctness often overcomes the benefits of theTLM-based design flow. In this paper we present a methodology toautomatically generate transactors for RTL IPs. We show how thetransactor code can be automatically generated by exploiting thetestbench of any RTL IP.