Fault injection is fundamental to evaluate the de- pendability of embedded software. Analyzing the interaction between the software and hardware components when hardware faults occur is efficient, but it is only possible once physical prototypes are available. On the other hand, fault injection on Hardware Description Language (HDL) models is a common practice that can significantly improve the verification phases, but HDL simulation speed constitutes a bottleneck of the design flow. In such a context, executing software on a virtual CPU providing fault-injection capabilities allows engineers to antic- ipate Embedded Software (ESW) dependability analysis at an earlier design stage. Thus, we present a non-intrusive approach that offers high speed for simulating hardware faults affecting CPU behaviors. This is obtained through dynamic translation of ESW binary code. In this work, hardware fault models (i.e., stuck-at, transient and delay faults) have been abstracted to an instruction-accurate CPU emulator without losing quality for ESW dependability analysis. Experimental results proves both the efficiency and effectiveness of the proposed approach.

Efficient Fault Simulation through Dynamic Binary Translation for Dependability Analysis of Embedded Software

FUMMI, Franco;PRAVADELLI, Graziano
2013

Abstract

Fault injection is fundamental to evaluate the de- pendability of embedded software. Analyzing the interaction between the software and hardware components when hardware faults occur is efficient, but it is only possible once physical prototypes are available. On the other hand, fault injection on Hardware Description Language (HDL) models is a common practice that can significantly improve the verification phases, but HDL simulation speed constitutes a bottleneck of the design flow. In such a context, executing software on a virtual CPU providing fault-injection capabilities allows engineers to antic- ipate Embedded Software (ESW) dependability analysis at an earlier design stage. Thus, we present a non-intrusive approach that offers high speed for simulating hardware faults affecting CPU behaviors. This is obtained through dynamic translation of ESW binary code. In this work, hardware fault models (i.e., stuck-at, transient and delay faults) have been abstracted to an instruction-accurate CPU emulator without losing quality for ESW dependability analysis. Experimental results proves both the efficiency and effectiveness of the proposed approach.
9781467363778
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Utilizza questo identificativo per citare o creare un link a questo documento: http://hdl.handle.net/11562/580750
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