The increasing prevalence of timing-related failures in integrated circuits makes delay-fault test generation extremely important in the design flow. However, delay test generation is a complex and computational-intensive activity, and it is feasible relatively later in the design process because of the need for low-level implementation details. In contrast, TLM system models are available from the early phases of the design process, but they lack the low-level details needed for delay test generation. In this paper, we first propose a high-level fault model capable of representing transition delay faults at TLM through mutation analysis. We then propose a test-generation methodology centered around this fault model. Its purpose is to reduce the complexity of test generation for transition delay faults for non-scan circuits. This is achieved by exploiting TLM simulation speed and early availability of TLM models in the design process. Experimental results highlight the effectiveness of the proposed methodology by achieving a speedup in CPU time in the range of one order of magnitude, and a 10% average increase in fault coverage.
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