The paper presents a novel abstraction methodology for generating time-and power-annotated TLM models from synthesizable RTL descriptions. Theproposed techniques allow the integration of existing RTL IP componentsinto virtual platforms for early software development and platform design,configuration, and exploration. With the proposed approach, IP models canbe natively integrated into SystemC TLM-2.0 platforms and executed 10-1000times faster compared to state-of-the-art RTL simulators. The abstractionmethodology guarantees preservation of the behaviour and timing of the RTLmodels. Target technology dependent power properties of IP components arerepresented as power state-machines and integrated into the abstracted TLMmodels. The experimental results show a relative error less than 10\% ofthe abstracted model's power consumption compared to state-of-the-art RTLpower simulators. The evaluation has been performed on RTL IP componentswith different characteristics and demonstrates the effectiveness of thepresented abstraction methodology.
File in questo prodotto:
Non ci sono file associati a questo prodotto.