Verification via fault injection and fault simulation is a widely adopted technique to evaluate the correctness of a design implementation. However, the complexity of industrial designs and the huge number of faults that must be injected into them require efficient fault simulators, in order to make verification via fault simulation an affordable task. To optimize fault simulation performances, some parallelization techniques have been proposed at gate level. On the contrary, they have not been fully exploited at RTL, where functional fault models, instead of gate-level ones, are considered. Thus, this paper analyzes the impact of such parallelization techniques on functional faults. In particular, possible issues are presented together with optimizations that can be implemented to speed up the simulation. Finally, experimental results are reported, which point out the role of parallelization in functional verification.
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