In this paper we present the Properties Specification Language (PSL) utilization in a system level verification flow for System on Chip (SoC) designs. A compositional approach is proposed and two property-based techniques are described and compared in terms of property refinement effort and simulation speed delay.
On the Property-based Verification in SoC Design Flow Founded on Transaction Level Modeling
BOMBIERI, Nicola;FUMMI, Franco
2005-01-01
Abstract
In this paper we present the Properties Specification Language (PSL) utilization in a system level verification flow for System on Chip (SoC) designs. A compositional approach is proposed and two property-based techniques are described and compared in terms of property refinement effort and simulation speed delay.
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