Simplifying Sequential gate-Level Test Generation Through Exploitation of High-Level Information

Sequential test generation for large and complex designs, when performed at the gate-level, is known to be a difficult task. Highlevel testing strategies, on the other hand, are less computation intensive, but suffer from accuracy problems. In this paper we propose to exploit high-level information to simplify gate-level test generation. In particular, we propose to compute a set of test sequences starting directly from the VHDL description of the system being synthesized, without any knowledge of the final realization of the design. Such test sequences are then simulated at the gate-level in order to reduce the number of faults for which a test needs to be determined by the gate-level test generation tool, thus allowing substantial time savings. Experimental results, though preliminary, show the effectiveness of the proposed technique.