Aim of this paper is to present a self-testable FIFO memory macrocell, which can be embedded into larger devices. A dual port RAM-type NFO has been designed. A new test procedure for the macrocell has been defined aiming at detecting all possible faults in the control logic and the RAM cell. Given such a test procedure the appropriate Built-in Self Test architecture has been defined, independently of the memory size. Fault coverage and area overhead for the proposed solution are presented.
A Parametric Design of a Built-In Self-Test FIFO Embedded Memory
FUMMI, Franco;
1996-01-01
Abstract
Aim of this paper is to present a self-testable FIFO memory macrocell, which can be embedded into larger devices. A dual port RAM-type NFO has been designed. A new test procedure for the macrocell has been defined aiming at detecting all possible faults in the control logic and the RAM cell. Given such a test procedure the appropriate Built-in Self Test architecture has been defined, independently of the memory size. Fault coverage and area overhead for the proposed solution are presented.
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