A Testing Methodology for VHDL Based High-Level Designs

The test problem increasingly affects system design process, related costs and time to market. Requirements from VLSI/WSI manufacturers are for fast and reliable testabilit y tools, with the possibilit y of their introduction in early phases of design. In this paper we describe the different abstraction levels at which testabilit y analysis will be applied in the REQUEST Project. The global tool-set architecture supporting this analysis will be introduced and commented. All design phases are included in this design flow, from the Data Flow Graph/Control Flow Graph (CDFG/CFG) representations of behaviors (directly derived from VHDL behavioral specifications), down to gate level. The paper will t hen present an application scenario for the behavioral level, where most of the innovative features have been introduced, including a new behavioral fault model strictly related to the lower levels of abstraction.