Control-dominated architectures are usually specified, in a hardware description language (HDL), by means of a composition of FSMs. This paper presents two FSM-based models which can be extracted from a Statechart or a HDL description. Such models are compared to the description of the device at the different abstraction levels of a standard synthesis flow. This comparison simplifies the testing problem producing a complete testing strategy that uses functional information to perform scan insertion, redundancies removal and test pattern generation even for devices which cannot be satisfactorily analyzed at the gate level.
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