Historically, the concept of stuck-on/off defect did not originate from physical observations but rather to model the behavior of faults at the gate level. Digital stuck-at fault models where a transistor is considered frozen in on-state or off-state may not apply well on analog circuits because even a slight variation could create deviations of several magnitudes. This implies that standard stuck-at faults would not be general enough for analog behavior, i.e., the transistor will not be stuck to have dI/dVg = 0.0. Recent works have suggested to consider physical phenomena, like modeling oxide defects into the transistor, less abstract with respect to digital stuck-at fault and analog stuck-on/off defect.This paper focuses on evaluating faults proposed by the IEEE P2427 standard, which is still a work-in-progress standard. Moreover, a novel approach is presented for modeling realistic stuck-on/off defects based on oxide defects. We investigate the impact of these faults on the circuit on two designs taken from the IEEE analog-benchmarks circuit collection: an operational amplifier and a comparator model. Furthermore, we apply a novel method that relies on AC matrices extracted at several operating points and combines it with a circle-fitting technique to compare faults with uncertain parameters.

Investigation on Realistic Stuck-on/off Defects to Complement IEEE P2427 Draft Standard

Sadia Azam;Nicola Dall'Ora
;
Enrico Fraccaroli;Franco Fummi
2022

Abstract

Historically, the concept of stuck-on/off defect did not originate from physical observations but rather to model the behavior of faults at the gate level. Digital stuck-at fault models where a transistor is considered frozen in on-state or off-state may not apply well on analog circuits because even a slight variation could create deviations of several magnitudes. This implies that standard stuck-at faults would not be general enough for analog behavior, i.e., the transistor will not be stuck to have dI/dVg = 0.0. Recent works have suggested to consider physical phenomena, like modeling oxide defects into the transistor, less abstract with respect to digital stuck-at fault and analog stuck-on/off defect.This paper focuses on evaluating faults proposed by the IEEE P2427 standard, which is still a work-in-progress standard. Moreover, a novel approach is presented for modeling realistic stuck-on/off defects based on oxide defects. We investigate the impact of these faults on the circuit on two designs taken from the IEEE analog-benchmarks circuit collection: an operational amplifier and a comparator model. Furthermore, we apply a novel method that relies on AC matrices extracted at several operating points and combines it with a circle-fitting technique to compare faults with uncertain parameters.
transistor-level fault simulation
fault grouping
Analog defect modeling
analog defect simulation
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11562/1069686
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