Sfoglia per Autore
Behavioral Test Generation for the Selection of BIST Logic
2002-01-01 G., Biasoli; F., Ferrandi; Fin, Alessandro; Fummi, Franco; D., Sciuto
On the Use of a Fault Model to Validate the Completeness of a Set of Properties
2002-01-01 A., Fedeli; Fummi, Franco; Pravadelli, Graziano; U., Rossi; F., Toto
A Fault Tolerant Incremental Design Methodology
2002-01-01 Cailotto, Stefano; Fin, Alessandro; Fummi, Franco
Legacy SystemC Co-Simulation of Multi-Processor Systems-on-Chip
2002-01-01 L., Benini; D., Bertozzi; Drago, Nicola; Fummi, Franco; Poncino, Massimo
A 1000X Speed Up for Properties Completeness Evaluation
2002-01-01 A., Castelnuovo; A., Fedeli; Fin, Alessandro; Fummi, Franco; Pravadelli, Graziano; U., Rossi; F., Sforza; F., Toto
An Error Simulation Based Approach to Measure Error Coverage of Formal Properties
2002-01-01 Azzoni, Paolo; A., Fedeli; Fummi, Franco; Pravadelli, Graziano; U., Rossi; F., Toto
A Genetic Testing Framework for Digital Integrated Circuits
2002-01-01 X., Yu; Fin, Alessandro; Fummi, Franco; E. M., Rudnick
Modeling Network Embedded Systems with NS-2 and SystemC
2002-01-01 Drago, Nicola; Fummi, Franco; Poncino, Massimo
Functional Test Generation: Overview and Proposal of a Hybrid Genetic Approach
2002-01-01 Ferrandi, F.; Fin, Alessandro; Fummi, Franco; Sciuto, D.
A Protected IP-Core Test Generation
2002-01-01 Fin, Alessandro; Fummi, Franco
A Remote Methodology for Embedded Systems Design and Validation
2003-01-01 Fin, Alessandro; Fummi, Franco
Identification of Design Erros through Functional Testing
2003-01-01 F., Ferrandi; Fummi, Franco; Pravadelli, Graziano; D., Sciuto
Laerte++: an Object Oriented High-Level TPG for SystemC Designs
2003-01-01 Fin, Alessandro; Fummi, Franco
Estimation of BUS Performance for a Tuplespace in an Embedded Architecture
2003-01-01 Drago, Nicola; Fummi, Franco; Poncino, Massimo; M., Monguzzi; Perbellini, Giovanni
On SAT-applicability to High-Level Testing
2003-01-01 E., Coltro; Fin, Alessandro; Fummi, Franco
The Confluence of Manufacturing Test and Design Validation
2003-01-01 Fummi, Franco
A Timing-Accurate Modeling and Simulation Environment for Networked Embedded Systems
2003-01-01 Fummi, Franco; P., Gallo; Martini, Stefano; Perbellini, Giovanni; Poncino, Massimo; F., Ricciato
Redundant Functional Faults Reduction by Saboteur Synthesis
2003-01-01 Fummi, Franco; Marconcini, Cristina; Pravadelli, Graziano
Genetic Algorithms: the Philosopher’s Stone or an Effective Solution for High-Level TPG?
2003-01-01 Fin, Alessandro; Fummi, Franco
A SystemC-based Framework for Properties Incompleteness Evaluation
2003-01-01 Fin, Alessandro; Fummi, Franco; Poncino, Massimo; Pravadelli, Graziano
Titolo | Data di pubblicazione | Autore(i) | File |
---|---|---|---|
Behavioral Test Generation for the Selection of BIST Logic | 1-gen-2002 | G., Biasoli; F., Ferrandi; Fin, Alessandro; Fummi, Franco; D., Sciuto | |
On the Use of a Fault Model to Validate the Completeness of a Set of Properties | 1-gen-2002 | A., Fedeli; Fummi, Franco; Pravadelli, Graziano; U., Rossi; F., Toto | |
A Fault Tolerant Incremental Design Methodology | 1-gen-2002 | Cailotto, Stefano; Fin, Alessandro; Fummi, Franco | |
Legacy SystemC Co-Simulation of Multi-Processor Systems-on-Chip | 1-gen-2002 | L., Benini; D., Bertozzi; Drago, Nicola; Fummi, Franco; Poncino, Massimo | |
A 1000X Speed Up for Properties Completeness Evaluation | 1-gen-2002 | A., Castelnuovo; A., Fedeli; Fin, Alessandro; Fummi, Franco; Pravadelli, Graziano; U., Rossi; F., Sforza; F., Toto | |
An Error Simulation Based Approach to Measure Error Coverage of Formal Properties | 1-gen-2002 | Azzoni, Paolo; A., Fedeli; Fummi, Franco; Pravadelli, Graziano; U., Rossi; F., Toto | |
A Genetic Testing Framework for Digital Integrated Circuits | 1-gen-2002 | X., Yu; Fin, Alessandro; Fummi, Franco; E. M., Rudnick | |
Modeling Network Embedded Systems with NS-2 and SystemC | 1-gen-2002 | Drago, Nicola; Fummi, Franco; Poncino, Massimo | |
Functional Test Generation: Overview and Proposal of a Hybrid Genetic Approach | 1-gen-2002 | Ferrandi, F.; Fin, Alessandro; Fummi, Franco; Sciuto, D. | |
A Protected IP-Core Test Generation | 1-gen-2002 | Fin, Alessandro; Fummi, Franco | |
A Remote Methodology for Embedded Systems Design and Validation | 1-gen-2003 | Fin, Alessandro; Fummi, Franco | |
Identification of Design Erros through Functional Testing | 1-gen-2003 | F., Ferrandi; Fummi, Franco; Pravadelli, Graziano; D., Sciuto | |
Laerte++: an Object Oriented High-Level TPG for SystemC Designs | 1-gen-2003 | Fin, Alessandro; Fummi, Franco | |
Estimation of BUS Performance for a Tuplespace in an Embedded Architecture | 1-gen-2003 | Drago, Nicola; Fummi, Franco; Poncino, Massimo; M., Monguzzi; Perbellini, Giovanni | |
On SAT-applicability to High-Level Testing | 1-gen-2003 | E., Coltro; Fin, Alessandro; Fummi, Franco | |
The Confluence of Manufacturing Test and Design Validation | 1-gen-2003 | Fummi, Franco | |
A Timing-Accurate Modeling and Simulation Environment for Networked Embedded Systems | 1-gen-2003 | Fummi, Franco; P., Gallo; Martini, Stefano; Perbellini, Giovanni; Poncino, Massimo; F., Ricciato | |
Redundant Functional Faults Reduction by Saboteur Synthesis | 1-gen-2003 | Fummi, Franco; Marconcini, Cristina; Pravadelli, Graziano | |
Genetic Algorithms: the Philosopher’s Stone or an Effective Solution for High-Level TPG? | 1-gen-2003 | Fin, Alessandro; Fummi, Franco | |
A SystemC-based Framework for Properties Incompleteness Evaluation | 1-gen-2003 | Fin, Alessandro; Fummi, Franco; Poncino, Massimo; Pravadelli, Graziano |
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