VILLA, Tiziano
VILLA, Tiziano
DIPARTIMENTO DI INGEGNERIA PER LA MEDICINA DI INNOVAZIONE
Advances in encoding for logic synthesis
2000-01-01 L., Lavagno; Villa, Tiziano; A., Sangiovanni Vincentelli
An Introduction to the Verification of Hybrid Systems using Ariadne
2015-01-01 Bresolin, Davide; Geretti, Luca; Villa, Tiziano; P., Collins
Formal Verification Applied to Robotic Surgery
2015-01-01 Bresolin, Davide; Geretti, Luca; Muradore, Riccardo; Fiorini, Paolo; Villa, Tiziano
Hardware equivalence and property verification
2010-01-01 Jiang, J. H. R.; Villa, Tiziano
Logic synthesis by signal-driven decomposition
2010-01-01 Bernasconi, A.; Ciriani, V.; Trucco, G.; Villa, Tiziano
Optimization of Synchronous Circuits
2001-01-01 S., Hassoun; Villa, Tiziano
Special issue: Formal verification of cyber-physical systems
2022-01-01 Geretti, Luca; Abate, Alessandro; Nuzzo, Pierluigi; Villa, Tiziano
Synthesis of complemented circuits
2018-01-01 Bernasconi, A.; Brayton, R.; Ciriani, V.; Trucco, G.; Villa, T.
Synthesis of multi-level Boolean networks
2010-01-01 Villa, Tiziano; Brayton, R.; Sangiovanni Vincentelli, A.
| Titolo | Data di pubblicazione | Autore(i) | File |
|---|---|---|---|
| Advances in encoding for logic synthesis | 1-gen-2000 | L., Lavagno; Villa, Tiziano; A., Sangiovanni Vincentelli | |
| An Introduction to the Verification of Hybrid Systems using Ariadne | 1-gen-2015 | Bresolin, Davide; Geretti, Luca; Villa, Tiziano; P., Collins | |
| Formal Verification Applied to Robotic Surgery | 1-gen-2015 | Bresolin, Davide; Geretti, Luca; Muradore, Riccardo; Fiorini, Paolo; Villa, Tiziano | |
| Hardware equivalence and property verification | 1-gen-2010 | Jiang, J. H. R.; Villa, Tiziano | |
| Logic synthesis by signal-driven decomposition | 1-gen-2010 | Bernasconi, A.; Ciriani, V.; Trucco, G.; Villa, Tiziano | |
| Optimization of Synchronous Circuits | 1-gen-2001 | S., Hassoun; Villa, Tiziano | |
| Special issue: Formal verification of cyber-physical systems | 1-gen-2022 | Geretti, Luca; Abate, Alessandro; Nuzzo, Pierluigi; Villa, Tiziano | |
| Synthesis of complemented circuits | 1-gen-2018 | Bernasconi, A.; Brayton, R.; Ciriani, V.; Trucco, G.; Villa, T. | |
| Synthesis of multi-level Boolean networks | 1-gen-2010 | Villa, Tiziano; Brayton, R.; Sangiovanni Vincentelli, A. |