Energy Aware TLM Platform Simulation via RTL Abstraction

Energy consumption estimation is nowadays one of the most pressing concerns in the design of embedded systems. In order to provide power estimates, techniques have been developed to enable energy-aware simulation of CPU models at different abstraction levels, such as register-transfer level (RTL) and software through an instruction set simulator (ISS). However, the chosen abstraction level heavily affects the outcome of the simulation in terms of speed and accuracy. RTL simulations are more accurate because of their wealth in terms of implementation details, but require significant computation times. ISS simulations run much faster, but are affected by a loss of accuracy due to their software implementation. Transaction-level modeling (TLM) simulations provides an ideal trade-off between speed and accuracy, but they rely on the creation of a TLM platform which is usually not available and must be manually created. In this context, we propose a methodology to automatically abstract a starting RTL CPU description into a corresponding TLM description. The abstraction methodology preserves details required to perform an energy-aware simulation, such as timing accuracy and instruction counts.