Sfoglia per Autore
An Approach to a Design for Testability Personal Consultant
1990-01-01 G., Buonanno; A., Burri; Fummi, Franco; D., Sciuto
Design Representation and Manipulation for High-Level Synthesis of DSP Algorithm
1992-01-01 A., Balboni; C., Costi; Fummi, Franco; M., Porta; V., Rampa; D., Sciuto
Two-Dimensional Sequential Array Architectures: Design for Testability and Reconfiguration Issues
1993-01-01 C., Bolchini; Fummi, Franco; D., Sciuto
Fault Detection in Sequential Circuits through Functional Testing
1993-01-01 G., Buonanno; Fummi, Franco; D., Sciuto
Functional Testing and Constrained Synthesis of Sequential Architectures
1993-01-01 G., Buonanno; Fummi, Franco; D., Sciuto
FSM Fault Models Impact on Test Performances
1993-01-01 C., Bolchini; Fummi, Franco
A Design Methodology for the Correct Specification of VLSI Systems
1993-01-01 C., Bolchini; M., Bombana; Fummi, Franco; P., Cavalloro; C., Costi; G., Zaza
Test Generation for Stuck-at and Gate-Delay Faults in Sequential Circuits: a Mixed Functional/Structural Method
1994-01-01 Fummi, Franco; D., Sciuto; M., Serra
Two-Dimensional Sequential Arrays: Design for Testability Approaches
1994-01-01 C., Bolchini; Fummi, Franco; D., Sciuto
From Behavioral Description to Systolic Array Based Architectures
1994-01-01 A., Balboni; C., Costi; Fummi, Franco; D., Sciuto
Behavioral Testability and Test Pattern Generation of the Hopfield Network Model
1994-01-01 C., Alippi; Fummi, Franco; V., Piuri; M., Sami; D., Sciuto
On the Detection of Delay Faults Starting from a Functional Description of a Sequential Circuit
1994-01-01 Fummi, Franco
A Functional Approach to Delay Fault Test Generation for Sequential Circuits
1994-01-01 Fummi, Franco; D., Sciuto; M., Serra
Design for Testability Issues in the Implementation of Sequential Array Architectures
1994-01-01 G., Bezzi; C., Bolchini; I., Bolzoni; S., Cantu`; Fummi, Franco; D., Sciuto
Functional Testing of Hopfield Networks: an FSM-Based Approach
1995-01-01 C., Alippi; Fummi, Franco; V., Piuri; M. G., Sami; D., Sciuto
Test Sequences Embedding with Cellular Automata
1995-01-01 Fummi, Franco; D., Sciuto; M., Serra
TIES: a Testability Increase Expert System for VLSI Design
1995-01-01 Buonanno, G; Fummi, Franco; Sciuto, D.
Testable Synthesis of High Complex Control Devices
1995-01-01 Fummi, Franco; U., Rovati; D., Sciuto
Sequential Logic Minimization Based on Functional Testability
1995-01-01 Fummi, Franco; D., Sciuto; M., Serra
Synthesis for Testability of Large Complexity Controllers
1995-01-01 Fummi, Franco; D., Sciuto; M., Serra
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